Clock generator circuits are typically employed to generate one or more clock output signals based upon a clock input signal. One drawback of conventional clock generator circuits (e.g., clock generator integrated circuits or chips) is their limited programmability.
For example, there is often limited programmability in terms of input/output signal types, input/output voltage levels, frequency range, and/or output banking structure. Furthermore, if programming is available, the programming may have to be performed by pin strapping, which is difficult to implement, inflexible, and may require the utilization of a number of pins.
Another drawback of conventional clock generator circuits is their lack of support for joint test action group (JTAG) or other automated testing. Consequently, it can often be cumbersome, time-consuming, and expensive to test a circuit board having clock generator circuits and other components (e.g., microprocessors, field programmable gate arrays (FPGAs), or complex programmable logic devices (CPLDs)). As a result, there is a need for improved clock generation techniques.